1. Technical Field
The present invention relates generally to an improved data processing system. More specifically, the present invention is directed to an improved apparatus and method for I/O address translation in order to specify a relaxed ordering for I/O accesses.
2. Description of Related Art
Operating systems are responsible for managing the virtual memory of a computer system. Virtual memory is addressable memory that extends beyond the limits of the available physical memory and is thus, “virtual.” The principal benefit of using virtual memory is that a user can run more applications at once and work with larger amounts of data than would be possible if the logical address space were limited to the available physical memory. Instead of equipping a computer with amounts of physical memory large enough to handle all possible needs, the user can install only enough physical memory to meet average needs. During those occasional times when more memory is needed for large tasks or many applications, the user can take advantage of virtual memory.
The operating system uses a Virtual Memory Manager (VMM) to perform virtual memory management. Virtual memory management involves the establishment of virtual address translations to real physical memory locations and the generation of data structures, referred to as “page frame tables” or simply “page tables,” which may be used to perform virtual to real address translations. The VMM also provides a number of routines that software can use to modify or obtain information about the software operations. For example, the VMM may be used to hold portions of the logical address space in physical memory, lock portions of the logical address space in their physical memory locations, determine whether a particular portion of the logical address space is currently in physical memory, and determine, from a logical address, the physical address of a block of memory.
The VMM extends the logical address space by using part of an available secondary storage, e.g., a hard disk, to hold portions of applications and data that are not currently in use in physical memory. When an application needs to operate on portions of memory that have been transferred to disk, the VMM loads those portions back into physical memory by making them trade places with other, unused segments of memory. This process of moving portions, or pages, of memory between physical RAM and the hard disk is called “paging.”
When a software component tries to access data in a page of memory that does not currently have a valid virtual to physical translation resident in the translation hardware, the CPU issues a special kind of bus error known as a “page fault.” Translation hardware is platform specific, but usually includes translation lookaside buffers (TLBs), which are caches used to hold the most recently used page table entries, and a hardware page frame table. A similar translation mechanism is also used for I/O access of memory.
The VMM intercepts page faults and tries to load the necessary translation into the hardware page frame table. In some cases not only does the referenced page not have a valid translation in the hardware page frame table, but is also not resident in physical memory. In this case, not only does the VMM have to load a valid translation into the hardware page table, but it must also load the affected page or pages into physical memory. The VMM does so by executing its own internal page-fault handler. This loading of the valid translation and affected pages takes additional processor cycles to perform and thus, is a source of latency in the operation of the processor of the computer system.
The handling of page faults is not the only source of latency in virtual memory computer systems. Congestion also results in latency in the computer system that causes the processor to execute instructions at a slower rate. That is, when there are read/write instructions accessing the same portions of memory as other read/write instructions, congestion occurs in that many accesses, from multiple processors or input/output (I/O) devices for example, to the same portion of memory are pending and must be executed in an ordered manner. Thus, because of congestion, a specific access may take more time to complete than accesses of a portion of memory that is less congested. If subsequent accesses to portions of memory with less congestion are unnecessarily delayed, such as because of the need to perform an access to a congested portion of memory first, overall performance of the computer system suffers. This is because various buffers and resources in the I/O subsystem are tied up longer than necessary and are, therefore, unavailable for use by subsequent I/O reads and writes.
In order to avoid such problems due to congestion, many processors include the capability to perform I/O reads and writes out-of-order whenever possible, i.e. the reads and writes are performed in the main memory in a different order from which an I/O device initiates the accesses. This is referred to as weak ordering of the reads and writes.
However, in some ordering schemes, the order in which reads and/or writes occur is essential to an underlying communication scheme. For example, in a producer-consumer protocol, one block of writes may convey data that was requested as part of an I/O operation request, such as a disk read. A subsequent write may indicate that the I/O operation has completed. For this protocol, it is essential that this last write be performed after all previous writes. This ordering is referred to as strong or strict ordering.
While weak ordering provides flexibility with the execution of reads and writes, there are times when such weak ordering may result in errors in the processing of reads and writes, i.e. when the order in which reads and/or writes are performed is important to proper operation of the system. While strong or strict ordering ensures proper operation of the system, such strong or strict ordering for all I/O operations may result in congestion, thereby reducing the speed at which I/O reads and writes may be performed.